Evaluation and optimization of replication algorithms for logic bipartitioning

Logic partitioning is an important area of VLSI CAD, and there have been numerous approaches proposed. Logic replication, the duplication of logic in order to minimize communication between partitions, can be an effective component of a complete partitioning solution. In this paper we seek a better understanding of the important issues in logic replication. By adding new optimizations to existing algorithms we are able to significantly improve the quality of these techniques, achieving up to 13.9% better results than the best existing replication techniques. When integrated into our already state-of-the-art (non-replication) partitioner, we improve overall cutsizes by 38.8%, while requiring the duplication of at most 7% of the logic.